Monday, 28 of July of 2014

HOW-TO: Stitching Vias in Eagle

Vias are conductive holes on a printed circuit board, used to electrically connect two layers of the circuit together. They serve several purposes, the most prominent of which is to move a trace from one layer to another, for example from top to bottom. This is useful because it allows the designer a great deal more flexibility during layout, and ultimately can help keep traces shorter by allowing more direct routing of signals, particularly with surface-mount designs.

Vias are also used to create structures called ‘via fences’, or ‘picket fences’, which help isolate different parts of the circuit from each other — for example, separating noisy, high-frequency digital or RF signals from lower-frequency, low-noise analog audio signals. In this form they are also placed around the periphery of the board to help reduce the amount of EMI radiated by a board, and to ensure that no traces end up near the edge of the board.

They can be used in a (loose or tight) grid structure — a ‘via bed’ or ‘copper mattress’ — to redundantly connect ground planes together, which reduces ground loops and ensures the shortest, lowest-impedance path to ground for all components. You can see an example of this in the lower-right corner of the photo of the Raspberry Pi Model B, above.

A non-electrical use for vias is as thermal relief. They can be used to transfer heat from one side of a board to another, or from an internal layer to the outside, and for dissipation as well. For a 1.6mm thick PCB, a 1mm diameter via has ~6.3 times the surface area of a 1mm diameter bare patch of copper (though less air flow across it, so a 630% increase is radiative dissipation is unlikely).

The process of laying down vias in fences and beds is sometimes known as ‘stitching’, because the final product resembles sewed fabric — tiny holes at regular intervals on the PCB. This is especially noticeable when the vias are covered in soldermask, as they are in the photo above.

There are a number of methods for stitching vias in Eagle, and some are more involved than others. Here, I’ll show you the method I use. For clarity, I’ll demonstrate using a 2-layer design, but this method will work for buried vias (between internal layers) and blind vias (surface to internal) as well.

1. Pour the Copper.

First, you need to create copper pours on the top and bottom and name them. Both layers have to have the same name in order for this process to work. Naming them identically tells Eagle that they’re both connected to the same electrical node. Let’s call both of them ground, or “GND”, using the NAME tool.

2. Place the proto-via.

Once both layers are named, throw down a single via, anywhere on the copper pour. For stiched vias used for fences and beds, smaller is usually better, size-wise. The minimum via size is usually dictated by the fab house who will be making your PCBs — this information is part of their ‘design rule’ spec. I use OSHPark for fabbing most of my prototype PCBs, and their minimum via size is 13mil. I usually go with a via size a little above the mininum, say 14 or 15 mil. If there’s a possibility that your board may go into production (at a fab other than your prototyping house), you won’t have to resize everything later.

Once you’ve placed the via, use the NAME tool on it, and give this via the same name as your two copper pours. Eagle may ask if you want to connect the via node (N$2 or something) to node GND — say ‘yes’.

3. Perforate to taste.

Now that you’ve got your GND via, you can use the COPY tool to copy it as many times as you like. In this case (below), I’ve laid out a loose picket fence tracking along the curved trace between R1 and C1. When you’re stitching these vias, it’s a good idea to run a Design Rule Check (DRC) periodically to make sure you’re maintaining minimum clearance between the via and surrounding components/traces.

If you’re laying out a mattress grid of vias, it can be tempting to use the GROUP and COPY GROUP commands to duplicate entire rows of the grid at a time. Unfortunately, this doesn’t work well in Eagle. When you copy a group, it gives the new group a new name. “GND” becomes “GND1″, which is a different electrical node. You’ll still have vias on the board, but they won’t be connected to the copper layers (because Eagle thinks they’re a different node). I find it’s generally easier to simply put the vias down one-by-one, which gives you more control over the layout anyway. Alternately, you can rename the cloned vias to “GND” (Eagle will ask you if you want to connect GND1 to GND).

If you find you’ve made a mistake and need to remove a via, use the RIPUP tool (not the DELETE tool) to remove it. Eagle will show you an “X” where the via used to be to indicate a broken connection. Use the RATSNEST tool to clear the “X”.

3a. Density.

How close you place the vias next to one another varies. Some board houses charge more based on the number of through-holes (including vias) in a design, while some do not — again, the board house you use for prototypes may not be the one you use for production; place all the vias you think you need to get the job done.

I typically use a spacing of between 0.08″ and 0.2″ (2 – 5mm) — usually 0.1″ — depending on the density of the other components on the board, how much ground current I’m expecting, etc. More current necessitates more vias, as do noisier circuits. Inductive switch-mode power supplies (buck, boost, SEPIC, etc.) in particular tend to make a lot of noise (and move a lot of current through ground), so put them in a cage.

If I’m using the vias to conduct or dissipate heat, I tend to go larger with the hole sizes and the spacing. I also don’t use stopmask on thermal vias, because stopmask traps heat.

 4. Stop mask or no stop mask?

By default, Eagle leaves the annular rings (the plated copper circles around the hole) of vias exposed (no stopmask) when it generates the gerber files for the board. You can change this behavior by altering the DRC file. In the board editor, go to “Tools | DRC” and then the “Masks” tab. Under “limit”, set the size to a number larger than the drill size you chose for your vias. When Eagle generates the gerbers now, it will place stop mask over the entire via. Don’t make the “limit” number too large, though, or you may end up covering component through-holes too.

If you want to turn off stopmask for a particular via, use the INFO tool on it and check “STOP” in the info panel. This will expose the entire annular ring, which is useful for thermal stuff, or if the via is doubling as a test point (p.s. don’t use vias as test points).

And that’s about it! Now you know how to make fences, mattresses and heatsinks with vias in Eagle. You can use this method for traces too, instead of polygon pours, just make sure you name the signal of the trace appropriately.

More Information:

Wikipedia article about via fences.

Anatomy of a plated through hole [PDF]


SHAMELESS PLUG: I am available for hire to do circuit design and layout and other electrical engineering consulting — send me an email if you’re interested. I also do product and event photography.

Good Advice


New Circuit: Atari “Punch” Console

This is my variation on the venerable Atari Punk Console circuit, which I call the Atari “Punch” Console. The output of the original APC is ‘punched up’ with 3 sub-octave square waves which add more harmonics into the mix, resulting in a fatter tone. The sub-octaves are generated with a CD4024 binary counter, and are then summed together. They are mixed into the output by way of R6, which varies between the pure ‘punk’ output of the 556, and an equal balance of the 556 and the suboctaves.

As drawn above, the circuit has a 2Vp-p output (+/-1 volt), suitable for connecting to a line-in, assuming the circuit is run off of 9V. However, replacing R11 with a larger value (3k3, 4k7, etc) will produce greater voltage swing at the output.

Get the schematic and board files (Eagle v6) at GitHub!

Parts list (Mouser Project Page):

I’ve actually had this circuit kicking around for a while but I never wrote it up or designed a proper PCB for it. I took advantage of some free time recently to do just that.

If you build it, drop me a note in the comments or on Twitter and let me know how it comes out!


shameless plug: I am available for hire to do circuit design and layout and other electrical engineering consulting — send me an email if you’re interested. I also do product and event photography.


“The Maker Movement”: Wall Art For Your Workbench — Prints Now Available!

I’m very happy to announce that prints of my photo “The Maker Movement“, shown above in mockup of the 10×20 Standout, are now available for purchase. As I wrote originally:

I’ve wanted to do a photograph which captured what I think of when I think of makers, and which makers themselves would enjoy as a work.

All of us started the same way — as curious kids (maybe big kids). At first, most of us were following in the path of someone else — along what feels like a straight, well-defined line. But there’s a point where things start to diverge, and we go off and do our own thing. That’s what making is all about, and that’s what I tried to capture here.

Symbolism aside, I just dig this image. I’d like to sell it as a print, with a portion of the proceeds going to charity. What I’d like to know from you is if you’d be interested in buying such a thing. It’s always hard to judge whether or not a print will sell, especially for the artist, who is often too close to the work to be objective — that’s what galleries and curators are for. But I don’t want this to be a gallery piece. I’d like it to be an affordable work that people can hang in their homes, hackerspaces, shops, or offices and enjoy, so I’m asking you directly.

Many thanks to everyone for your compliments and support! It’s been a long time coming, but it’s finally here (yay!) — head on over to the SmugMug page to check it out!


PCB Layout: Why Vias Under Pads are a Bad Idea

I was going to write a long-winded introduction here, but then I changed my mind. Instead, I’ll just jump right in and say ‘don’t do this‘:

By ‘this’, I mean don’t place vias under pads*. All the offending pads above are connected to the ground plane, as they should be. However, placing the via directly under the pad is a bad idea. It’s tempting to do something like this when you’re trying to keep the size of your board small and you don’t have a lot of room to play around. Or maybe you just wanna be clever. Electrically, the idea is sound, but in practice it can be more trouble than it’s worth. When you get to the assembly stage and beyond, this can cause problems.

Heat, the engineer’s ancient and wily foe, has a hand in things here (naturally).

Let’s say you’re assembling this board by hand, and you get to working on pin 2 of the MCP1703 above. This pin is connected to ground, which on this board is a copper pour roughly the size of the board itself. That’s a lot of copper, and it’s going to radiate a lot of heat. When you touch your iron to this pad, the heat is conducted through the via and then radiated off the backside of the board. Your iron is basically dumping heat into this thing, because a significant portion is being radiated away by the ground plane. As a result, the temperature at the actual pad may be lower than it’s supposed to be. It may still be hot enough to just melt the solder and make it flow, but not enough to make it properly flow and form a good, wet bond.

At the same time, some of that solder is flowing into the hole in the via, conducting even more heat straight to the ground plane (instead of to the joint), so the problem rapidly escalates. In this case, you will have to dwell there a bit with your iron, and perhaps even set it slightly over temp, in order to get the solder to flow properly. Otherwise, you might find yourself with a nice cold-solder joint on your supply bypass capacitor, and a very noisy power rail.

Now let’s say you’re running this board through a reflow process instead. The reflow curves given in datasheets and other dox rarely take this sort of topology into account — and never explicitly, so you might need to adjust the ‘soak’ time accordingly. Unless you’re a metallurgist, you lack a reliable way to characterize the problem, so you’ll have to find the new soak time through trial and error.

This isn’t such a problem with one-offs, where you can take as much time as you need. However, in volume production, you don’t have time to be doing empirical soak tests. And anyway, extending the soak time means less units per hour, which lowers overall production efficiency.

The other reflow method — skillet — is quite the opposite. Assuming the ground plane is on the bottom, the pad connected to ground will actually get hotter than the other pads more quickly, and the situation will be reversed.

Finally, this situation will make rework an absolute nightmare — one terminal of the device will be sinking a lot more heat than the other. This is not a situation hot tweezers are designed to handle well. Hot air might be a little better, but it’s still going to be difficult.

The problem of supply planes sucking up heat has been known since the thru-hole days. The solution was to create thermals, which you can see within the bright red circle in the image below:

 The capacitor terminal above is connected to the positive supply plane by way of thermals. That is, it’s connected by three distinct traces, rather than all around the perimeter of the pad. The thermals impose a restriction on heat flow, so that the pad can heat up to proper temp, and the solder can flow and bond correctly. Just like electrical resistance, thermal resistance is proportional to the cross-sectional area of the conductor. Most EDA programs (including Eagle, shown here) will automatically create thermals on pads connected to supply planes, unless you specify otherwise. AFAIK, there is no way to get Eagle to automatically create thermals on vias. Note here that I’m not talking about ‘thermal vias‘, which are something completely different.

So what should you do? The simplest solution is to create your own thermals by running a trace between the pad and the via. It’s not hard — you just have to get over your inclination to make things As Small As Possible. The trace doesn’t need to be very long — the example shown above is actually exaggerated a bit to illustrate the concept. The main idea is that at no point should the via and the pad overlap.  The trace shouldn’t be too thin either, especially for a supply pin. Confer with this trace calculator to get a better idea: don’t forget you want to rate the trace for the maximum expected current, not the average current.

A tenth of an inch or two with a trace-width of 12-16 mils should do for most chips. Chips handling larger currents will require larger traces, or multiple small traces — you may end up having to trick your software into doing this by running multiple traces before you place the vias. It might give you grief in the meantime, but just ignore it. In the end, it’s worth it because you’ll have more balanced thermal conduction on your board.

And now you know.

*- There are certain circumstances in which vias-under-pads are necessary and useful, such as with dense BGA packages. In this case the vias have thermals connecting them to the plane for the reasons mentioned above. Chances are, if you’re working with this kind of technology, you don’t need to read my little tutorial here.

BB-313 PCBs Now Available

I am happy to announce that I am now selling PCBs for my BB-313 project. Since first announcing the design back in February, I’ve gotten several emails a week enquiring about PCBs, so I decided to go for it and start selling them.

These are nice, lead-free boards with a good-quality silkscreen, and they’re available in any color you want, as long as it’s green. Boards are $5/each + $2.50 shipping within the US. International shipping is $5.00 for up to 15 PCBs — this is automatically applied at checkout.

You can read all about the BB-313 at the project page, which also contains a cross-referenced BOM and Mouser project that makes it easy to get all the components required to build one. The BB-313 is Open Source Hardware, so you can make your own boards if you prefer.

Please note that I’m only selling PCBs right now, not kits.

UPDATE: I’ve now got it set up to apply the correct shipping for domestic and international orders, and to accept quantities greater than one.

Art for the Maker Movement

This is an idea I’ve been kicking around for awhile — I’ve wanted to do a photograph which captured what I think of when I think of makers, and which makers themselves would enjoy as a work.

All of us started the same way — as curious kids (maybe big kids). At first, most of us were following in the path of someone else — along what feels like a straight, well-defined line. But there’s a point where things start to diverge, and we go off and do our own thing. That’s what making is all about, and that’s what I tried to capture here.

Symbolism aside, I just dig this image. I’d like to sell it as a print, with a portion of the proceeds going to charity. What I’d like to know from you is if you’d be interested in buying such a thing. It’s always hard to judge whether or not a print will sell, especially for the artist, who is often too close to the work to be objective — that’s what galleries and curators are for. But I don’t want this to be a gallery piece. I’d like it to be an affordable work that people can hang in their homes, hackerspaces, shops, or offices and enjoy, so I’m asking you directly.

This would be an 8×12 digital c-print, matted to 6×10, without a frame. The image above is a mockup of the final print in a frame. You can see a larger version of the image here. The price would be no more than $30/print and would include a custom matte.

Please respond in the comments if you’re interested.

UPDATE: Wow! Thank you all so much for your enthusiastic response! I’m currently working out distribution (shipping cost, setting up a shop, etc.) but it looks like this could really happen. Prepping the image for print takes some time too, because I set very high standards for myself when it comes to prints. Thanks again for your amazing comments and encouragement — they mean a lot to me!

Arduino Leonardo Pinout Reference

I made this Arduino Leonardo pinout reference for anyone considering building shields for the Leonardo. Please note that shields designed for the UNO, Duemilanove, Diecimila and others will most likely NOT WORK on the Leonardo, because a lot of the pin functions have been moved around. This image helps you see some of the differences.

For example, the lower 8 digital pins are no longer all a single port, and many of the pins, with the exception of the RX and TX lines, are moved around. Some of the PWM lines are in the same place, but are now connected to different ports and OC registers than they were before.

On the other hand, you now have access to twice as many ADC pins as you did before, and you don’t have to give up 2 ADCs for I2C. You also get two more low-level interrupt lines and, of course, USB native functionality, which (I personally feel) is exciting!

You can see the full-size image (about 2200×1600) in my Flickr photostream. This pinout was derived from the info found here. The Leonardo image is from the official Arduino Leonardo page.

Happy hacking!

New Arduino Library: INA219 i2c Current/Power Monitor

I’m happy to announce a new Arduino library –  my first ever — for the TI INA219 current/power monitor chip. This is a neat little chip that has an isolated shunt voltage amplifier tied to a 12-bit delta-sigma converter. It has on-board oversampling (up to 128 samples) and is addressable over I²C. The I²C is handled by the Arduino Wire library.

The INA219 can provide the four main figures of interest for a DC bus: shunt voltage, bus voltage, load current and power. Note that it will not work with AC — it cannot calculate RMS values, or account for lead/lag phasing due to reactive loads — but it’s still super handy for monitoring the power consumption of circuits with DC rails.

You can download the library and an example sketch over on GitHub.

Happy current sensing!


Eico 377 Audio Generator, Part I

This weekend I picked up a very nice Eico 377 Audio Generator. When I first took it home on Saturday, I fired it up and checked it on the scope. The output looked good — the only thing amiss was a burned out power indicator lamp. I figured that could be easily replaced, so I set it aside and left it until Monday. On Monday, I took the unit apart to replace the lamp:

(Yes, it’s supposed to look like that.) In case you’re wondering about the light bulb, it’s part of the Wien bridge oscillator circuit. The negative resistance of the lamp acts as a variable parasitic path to ground — it keeps the gain around the feedback loop steady at 1 (unity), so that the ringing never saturates or dies out. The light bulb resistance is a clever hack originally invented by Bill Hewlett of Hewlett-Packard — since its introduction in the 1940′s, it became the standard topology for many Audio/IF oscillator circuits.

After replacing the power indicator bulb, I turned the unit back on to play around with it some more. On start up it worked fine, as it had on Saturday. I left the room for a few minutes to let it stabilize, and when I came back, the output was different. It looked like the top trace in this image:

Bear in mind that the scale in the bottom trace is off by a factor of 10. It reads as 5V/div, but it’s actually 50V/div. The Tek scope is not detecting that the HP probe used here is a 10x type, so it’s not correcting the scale.

I suspect that at some point while I was out of the room, something went amiss inside the output buffer tube (V-4 in the schematic).

(schematic from this schematic is actually from an earlier version of this unit — my unit has a dual-ganged vari-cap (not quad-ganged as shown here) and different range selector resistor values, but other than that the circuit is the same.

The bottom trace in the scope image above is from the wiper of pot R22, which is just to the left of V-4, beyond the coupling cap C-14. Pot R22 is the amplitude pot on the front panel. As you can see, the bottom trace is a nice, clean sine wave, so V-4 is getting a decent input, but it’s putting out garbage. This garbage has a characteristic though — you can see how the ‘spike’ in the output is aligned perfectly with the crown of the sine wave of the bottom trace. Obviously, there’s some rectifier action going on. Only at the peak of the waveform is there enough potential to push beyond the threshold and cause some current to flow at the v-4 cathode (the output). I

This leads me to believe that V-4 is either very weak, or completely bad. I tested the tube down at the local electronics shop, and it tested right on border of ‘good’ and ‘weak’, so it’s probably not entirely dead, but it still has some problems. I have no idea when that tester was last calibrated, though, so it could be totally shot. I’ll hopefully be getting a replacement tube next week, so then I’ll know for sure if it’s the tube or something else. It may also be one (or more) of the passive elements around the tube, but I doubt it. I checked them (with the tube removed) and they seem to align with the values printed on the sides, but you never know.

In the meantime, we can look at the schematic to get a basic idea of how it works. This is what I’ve figured out so far:

V-1 (6SJ7) is the active element in the Wien bridge oscillator.

V-2 is a buffer for the oscillator, which makes sense because you wouldn’t want to load the Wien bridge directly.

S-3 is the waveform switch, which selects between sine and square wave output. When ‘sine’ is selected, the V-2 output is routed directly to V-4 input via the R22 amplitude pot. When ‘square’ is selected, the V-2 output goes to V-3, which acts as a schmitt trigger to produce a square wave from the sinusoidal input. The output of V-3 is then routed to V-4, the output buffer (again via R22), which is where I suspect the problem is. Here’s the square wave version of the scope capture above:

Again, the input to V-4 is shown on the bottom (but the V/div scale is off, it’s actually 50V/div), and the output is shown on top. The jitter is caused by variations coupled in from the power rail.

One final interesting note is that the suppressor (topmost) grid of V-4 is not connected to anything, so this pentode is basically acting as a beam tetrode. In fact, both 6K6 tubes (V-2 and V-4) leave the suppressor unconnected, so I’m guessing the designers simply used this tube because it was cheaper (for them, at least — perhaps they had a lot of them in stock) than a dedicated beam tetrode.

So, that’s it for now. Hopefully I’ll get this output issue fixed by next week and I can share some more pictures.

The entire photo set is here.