What I did instead of watching the super bowl. A 36-hour personal hardware hackaton.
Date: 6 February, 2015
Categories: EE - project & practice
Friday, 3 of July of 2015
small-scale engineering with a sense of humor
What I did instead of watching the super bowl. A 36-hour personal hardware hackaton.
Date: 6 February, 2015
Categories: EE - project & practice
Differential equations are simple and elegant things. They describe the behavior of phenomena in the most ideal form. In that ideal form they are easy to understand and solve, once you comprehend the language used to express them. But for solving practical problems they are, in and of themselves, a non-starter. In order to make them useful to us, we have to apply boundary conditions to describe the particulars of the situation we wish to know more about.
The heat equation is a great example. It describes the distribution of thermal energy in some region over time, and it does a really good job of that. But what if we don’t want to just know the general rule for heat distribution in the universe — we want to know how heat will be distributed along a motorcycle exhaust pipe from manifold to tip. Specifically, we want to know what the temperature of the pipe will be at the point where it crosses the rider’s leg, 10 minutes after the engine is started. Enter boundary conditions. The boundary conditions describe the shape and contours of the pipe, and the thermal properties of the steel and chrome used to make it. We then take this mathematical description of the pipe and stick it into the heat equation to it to get the answer to our question.
Except it’s not as simple as just substituting one function into another and solving for X. There is no single X. The whole damn thing is X. The heat equation is a differential equation, which means the value at one point is based on the values at all the other points over time, so you have to solve the whole thing at once. It gets very involved very quickly. I won’t get in to the nuts and bolts of how this is done — basically you start out solving for a handful of points, and then keep splitting things into smaller and smaller pieces and solving those. It’s a conceptually simple, but arithmetically intense process — a lot of grunt work. (now easily performed by computers, but still).
Date: 7 November, 2014
Categories: EE - theory & design
One other feature that I like about this device is that unlike nearly every other VFD tube, the IVL2-7/5 has no opaque or diffuse backing behind the digits. It’s completely transparent front to back, which means that if you put it on top of a circuit board, you can (with a bit of backlighting) see the PCB below.
The circuit is pretty straightforward. The core is an Atmel ATMega88 AVR, and the real-time clock is a Maxim DS3231. The DS3231 is nice because it’s an all-in-one solution: it has a 32kHz temperature-compensated crystal and capacitors built in, so the only external component required is the backup battery. However, the DS3231 is pretty expensive. I happen to have a tube of them left over from another project, so I decided to use it in this design. There are other, much less expensive RTCs available which would work quite as well (BYO crystal, though).
The VFD display is driven by a Maxim MAX6920 — a 12-bit shift register with high-voltage (up to 76V) outputs. The 12-bit field is designed specifically for driving 4-digit clock displays (4 digit channels and 8 segment channels). It’s easy to use and very reliable and compact. It really is the only chip of its kind, so it’s a tad expensive. It’s also possible to drive the VFDs using a bunch of discrete components, but that was impractical here due to space constraints. If you’re interested in that, you should check out Riad Wahby’s excellent inGrid clock build, which describes his discrete HV driver circuit in some detail.
The circuit is powered from 3 voltage rails. The first is the battery voltage itself, which is used to drive the display filament (switched by the micro with a low-side MMBTA42 NPN). The battery voltage also feeds into the 5V boost converter (MCP1640 SOT23-6), which drives the #2 rail. This 2nd rail powers the AVR, DS3231, and MAX6920 logic, as well as acting as the input voltage to the second boost converter (NCP1403 SOT23-5), which produces the 13.5V VFD grid voltage (the third rail). The NCP1403 is enabled/disabled by the microcontroller, so it’s only in operation when the display is lit, which helps limit current draw from the battery.
I included jumpers (0805 pads) on the board so that I could switch the filament power from the battery to the 5V rail, in series with a current limiting resistor. In this configuration, the filament stays at a steady brightness for the life of the battery, and the display is brighter. However, the load on the 5V rail is higher, and considerable power is wasted as heat through this resistor, so the battery life is significantly shortened.
Also included on the board are a number of sensors: one analog and two digital. The analog sensor is a phototransistor used to detect the ambient light level (Q2). The digital sensors include a BMP180 barometric/temperature sensor and a MMA8653 accelerometer, to detect movement. Neither of these are populated in the photos above, though I may decide to add them in the future. Both digital sensors share the I2C bus with the DS3231, and an I2C breakout is provided on the bottom-left edge of the board, for troubleshooting or expansion purposes.
Other headers on the board include a 6-pin FTDI serial block, breakouts for two AVR ADC inputs (one is used by Q2), and test points for the battery voltage and boost converters. The AVR ISP 6-pin header is on the underside of the board beneath the display, to allow programming after assembly is complete.
The cage is built from extruded brass tubing — sometimes called ‘telescoping’ tubing, because each size nests inside the next size up, with a clearance of less than 5 mils. This makes it well-suited to the type construction used here: thinner straight pieces fitted into slightly larger elbows. This brass tube is commonly available from hobby and train stores (and Amazon), and it’s used often for scratch-building model engines and locomotives. It’s available in every size from ID=1/32″ to ID 1/2″.
I made the elbow pieces using 1/8″ OD stock in an inexpensive tube bender. As purchased, this tubing arrives in a hardened state, so when it’s used in the tube bender, the wall tends to collapse a little bit — note the dimples on the outer surface of the elbow pieces. If I wanted to maintain the integrity of the tube during a bend, I’d have annealed the tubing first. However, I needed a tighter turn radius than you’d get with annealed tubing, so I didn’t bother. Structurally, it’s still strong enough for what I need it to do. If I wanted to reinforce the corners, I could always place a solder fillet on the inside of the bend.
The roll cage is soldered to the PCB at four points — plated through-holes slightly larger than the OD of the straight brass tubing. This allowed me to plan the placement of the cage during PCB layout, and also allowed me to use one of my spare PCBs as a precise fixturing jig while I put together the various pieces of the cage.
To make the elbows I placed a full (or near full) length piece of stock in the tube bender, bent it to 90 degrees, and then trimmed off the bulk of the excess length with a hacksaw. I then used various needle files to dress it down to the proper size, and clean up the rough edges. There’s enough slack length in the design that didn’t have to precisely match all of the elbows to the same size, though I did try to get them close. Likewise, the straight pieces were cut to approximate size using the hacksaw, and the ends dressed appropriately.
The watch band for this project is a leather cuff I bought on Amazon. I like it because it looks good, has multiple mounting points (if you’re creative), and it’s comfortable to wear. The three straps on the cuff are handy because I can adjust for the taper of my forearm and it still fits well.
I went through several iterations and experiments before I finally settled on a method to mount the PCB to the cuff that provided enough flexibility, while at the same time ensuring a secure fit. The method I settled on was what I call an underslung loop (photo above).
At the top and bottom edges of the PCB, on the underside, there are two 1.25″ strips of bare copper (courtesy of a polygon on the bottom stopmask layer). Soldered to this is a piece of the thinner brass tube stock. Looped around these are the two strap loops, made of 12AWG solid conductor household wire. Both of these loops fit onto the center strap at the smaller openings on the sides of the cuff. The top loop is a bit longer than the bottom loop so that the watch has a slight cant towards the user when worn. When the cuff is removed, the loops hinge out a bit so that the whole thing lays flat. Removing the PCB from the cuff is just a matter of pulling out the center strap — reattaching means rethreading the whole thing, but this is pretty quick and easy too.
Tools and Materials
The following mechanical materials were used to build this project.
Wow — I’m quite overwhelmed by the response this project has received! In addition to making the front page of Reddit, there have been a few articles about it. Here’s a partial list:
I’m a freelance electrical engineer based in New York City. I’m currently looking to work with startups and agencies in every stage from concept to prototype to manufacturing; I’m particularly interested in the wearables and internet-of-things space. If you’re interested in working together, get in touch: email, Twitter or LinkedIn.
Date: 21 October, 2014
Categories: EE - project & practice
— John De Cristofaro (@johngineer) September 18, 2014
I’ll be at World Maker Faire in Queens, NY handing out biz cards with some neat pocket-sized hacker artwork. Find me there on Sunday to get one (while supplies last!).
I’ve also set up a coupon code for the poster-sized version of that image. Use the code* MFNY14 at checkout to get 14.04% off that print in any available size!
*-code expires 10/1.
Date: 19 September, 2014
Vias are conductive holes on a printed circuit board, used to electrically connect two layers of the circuit together. They serve several purposes, the most prominent of which is to move a trace from one layer to another, for example from top to bottom. This is useful because it allows the designer a great deal more flexibility during layout, and ultimately can help keep traces shorter by allowing more direct routing of signals, particularly with surface-mount designs.
Vias are also used to create structures called ‘via fences’, or ‘picket fences’, which help isolate different parts of the circuit from each other — for example, separating noisy, high-frequency digital or RF signals from lower-frequency, low-noise analog audio signals. In this form they are also placed around the periphery of the board to help reduce the amount of EMI radiated by a board, and to ensure that no traces end up near the edge of the board.
They can be used in a (loose or tight) grid structure — a ‘via bed’ or ‘copper mattress’ — to redundantly connect ground planes together, which reduces ground loops and ensures the shortest, lowest-impedance path to ground for all components. You can see an example of this in the lower-right corner of the photo of the Raspberry Pi Model B, above.
A non-electrical use for vias is as thermal relief. They can be used to transfer heat from one side of a board to another, or from an internal layer to the outside, and for dissipation as well. For a 1.6mm thick PCB, a 1mm diameter via has ~6.3 times the surface area of a 1mm diameter bare patch of copper (though less air flow across it, so a 630% increase is radiative dissipation is unlikely).
The process of laying down vias in fences and beds is sometimes known as ‘stitching’, because the final product resembles sewed fabric — tiny holes at regular intervals on the PCB. This is especially noticeable when the vias are covered in soldermask, as they are in the photo above.
There are a number of methods for stitching vias in Eagle, and some are more involved than others. Here, I’ll show you the method I use. For clarity, I’ll demonstrate using a 2-layer design, but this method will work for buried vias (between internal layers) and blind vias (surface to internal) as well.
1. Pour the Copper.
First, you need to create copper pours on the top and bottom and name them. Both layers have to have the same name in order for this process to work. Naming them identically tells Eagle that they’re both connected to the same electrical node. Let’s call both of them ground, or “GND”, using the NAME tool.
2. Place the proto-via.
Once both layers are named, throw down a single via, anywhere on the copper pour. For stiched vias used for fences and beds, smaller is usually better, size-wise. The minimum via size is usually dictated by the fab house who will be making your PCBs — this information is part of their ‘design rule’ spec. I use OSHPark for fabbing most of my prototype PCBs, and their minimum via size is 13mil. I usually go with a via size a little above the mininum, say 14 or 15 mil. If there’s a possibility that your board may go into production (at a fab other than your prototyping house), you won’t have to resize everything later.
Once you’ve placed the via, use the NAME tool on it, and give this via the same name as your two copper pours. Eagle may ask if you want to connect the via node (N$2 or something) to node GND — say ‘yes’.
3. Perforate to taste.
Now that you’ve got your GND via, you can use the COPY tool to copy it as many times as you like. In this case (below), I’ve laid out a loose picket fence tracking along the curved trace between R1 and C1. When you’re stitching these vias, it’s a good idea to run a Design Rule Check (DRC) periodically to make sure you’re maintaining minimum clearance between the via and surrounding components/traces.
If you’re laying out a mattress grid of vias, it can be tempting to use the GROUP and COPY GROUP commands to duplicate entire rows of the grid at a time. Unfortunately, this doesn’t work well in Eagle. When you copy a group, it gives the new group a new name. “GND” becomes “GND1″, which is a different electrical node. You’ll still have vias on the board, but they won’t be connected to the copper layers (because Eagle thinks they’re a different node). I find it’s generally easier to simply put the vias down one-by-one, which gives you more control over the layout anyway. Alternately, you can rename the cloned vias to “GND” (Eagle will ask you if you want to connect GND1 to GND).
If you find you’ve made a mistake and need to remove a via, use the RIPUP tool (not the DELETE tool) to remove it. Eagle will show you an “X” where the via used to be to indicate a broken connection. Use the RATSNEST tool to clear the “X”.
How close you place the vias next to one another varies. Some board houses charge more based on the number of through-holes (including vias) in a design, while some do not — again, the board house you use for prototypes may not be the one you use for production; place all the vias you think you need to get the job done.
I typically use a spacing of between 0.08″ and 0.2″ (2 – 5mm) — usually 0.1″ — depending on the density of the other components on the board, how much ground current I’m expecting, etc. More current necessitates more vias, as do noisier circuits. Inductive switch-mode power supplies (buck, boost, SEPIC, etc.) in particular tend to make a lot of noise (and move a lot of current through ground), so put them in a cage.
If I’m using the vias to conduct or dissipate heat, I tend to go larger with the hole sizes and the spacing. I also don’t use stopmask on thermal vias, because stopmask traps heat.
4. Stop mask or no stop mask?
By default, Eagle leaves the annular rings (the plated copper circles around the hole) of vias exposed (no stopmask) when it generates the gerber files for the board. You can change this behavior by altering the DRC file. In the board editor, go to “Tools | DRC” and then the “Masks” tab. Under “limit”, set the size to a number larger than the drill size you chose for your vias. When Eagle generates the gerbers now, it will place stop mask over the entire via. Don’t make the “limit” number too large, though, or you may end up covering component through-holes too.
If you want to turn off stopmask for a particular via, use the INFO tool on it and check “STOP” in the info panel. This will expose the entire annular ring, which is useful for thermal stuff, or if the via is doubling as a test point (p.s. don’t use vias as test points).
And that’s about it! Now you know how to make fences, mattresses and heatsinks with vias in Eagle. You can use this method for traces too, instead of polygon pours, just make sure you name the signal of the trace appropriately.
This is my variation on the venerable Atari Punk Console circuit, which I call the Atari “Punch” Console. The output of the original APC is ‘punched up’ with 3 sub-octave square waves which add more harmonics into the mix, resulting in a fatter tone. The sub-octaves are generated with a CD4024 binary counter, and are then summed together. They are mixed into the output by way of R6, which varies between the pure ‘punk’ output of the 556, and an equal balance of the 556 and the suboctaves.
As drawn above, the circuit has a 2Vp-p output (+/-1 volt), suitable for connecting to a line-in, assuming the circuit is run off of 9V. However, replacing R11 with a larger value (3k3, 4k7, etc) will produce greater voltage swing at the output.
Get the schematic and board files (Eagle v6) at GitHub!
Parts list (Mouser Project Page):
I’ve actually had this circuit kicking around for a while but I never wrote it up or designed a proper PCB for it. I took advantage of some free time recently to do just that.
If you build it, drop me a note in the comments or on Twitter and let me know how it comes out!
I’ve wanted to do a photograph which captured what I think of when I think of makers, and which makers themselves would enjoy as a work.
All of us started the same way — as curious kids (maybe big kids). At first, most of us were following in the path of someone else — along what feels like a straight, well-defined line. But there’s a point where things start to diverge, and we go off and do our own thing. That’s what making is all about, and that’s what I tried to capture here.
Symbolism aside, I just dig this image. I’d like to sell it as a print, with a portion of the proceeds going to charity. What I’d like to know from you is if you’d be interested in buying such a thing. It’s always hard to judge whether or not a print will sell, especially for the artist, who is often too close to the work to be objective — that’s what galleries and curators are for. But I don’t want this to be a gallery piece. I’d like it to be an affordable work that people can hang in their homes, hackerspaces, shops, or offices and enjoy, so I’m asking you directly.
Many thanks to everyone for your compliments and support! It’s been a long time coming, but it’s finally here (yay!) — head on over to the SmugMug page to check it out!
Date: 16 April, 2014
I was going to write a long-winded introduction here, but then I changed my mind. Instead, I’ll just jump right in and say ‘don’t do this‘:
By ‘this’, I mean don’t place vias under pads*. All the offending pads above are connected to the ground plane, as they should be. However, placing the via directly under the pad is a bad idea. It’s tempting to do something like this when you’re trying to keep the size of your board small and you don’t have a lot of room to play around. Or maybe you just wanna be clever. Electrically, the idea is sound, but in practice it can be more trouble than it’s worth. When you get to the assembly stage and beyond, this can cause problems.
Heat, the engineer’s ancient and wily foe, has a hand in things here (naturally).
Let’s say you’re assembling this board by hand, and you get to working on pin 2 of the MCP1703 above. This pin is connected to ground, which on this board is a copper pour roughly the size of the board itself. That’s a lot of copper, and it’s going to radiate a lot of heat. When you touch your iron to this pad, the heat is conducted through the via and then radiated off the backside of the board. Your iron is basically dumping heat into this thing, because a significant portion is being radiated away by the ground plane. As a result, the temperature at the actual pad may be lower than it’s supposed to be. It may still be hot enough to just melt the solder and make it flow, but not enough to make it properly flow and form a good, wet bond.
At the same time, some of that solder is flowing into the hole in the via, conducting even more heat straight to the ground plane (instead of to the joint), so the problem rapidly escalates. In this case, you will have to dwell there a bit with your iron, and perhaps even set it slightly over temp, in order to get the solder to flow properly. Otherwise, you might find yourself with a nice cold-solder joint on your supply bypass capacitor, and a very noisy power rail.
Now let’s say you’re running this board through a reflow process instead. The reflow curves given in datasheets and other dox rarely take this sort of topology into account — and never explicitly, so you might need to adjust the ‘soak’ time accordingly. Unless you’re a metallurgist, you lack a reliable way to characterize the problem, so you’ll have to find the new soak time through trial and error.
This isn’t such a problem with one-offs, where you can take as much time as you need. However, in volume production, you don’t have time to be doing empirical soak tests. And anyway, extending the soak time means less units per hour, which lowers overall production efficiency.
The other reflow method — skillet — is quite the opposite. Assuming the ground plane is on the bottom, the pad connected to ground will actually get hotter than the other pads more quickly, and the situation will be reversed.
Finally, this situation will make rework an absolute nightmare — one terminal of the device will be sinking a lot more heat than the other. This is not a situation hot tweezers are designed to handle well. Hot air might be a little better, but it’s still going to be difficult.
The problem of supply planes sucking up heat has been known since the thru-hole days. The solution was to create thermals, which you can see within the bright red circle in the image below:
The capacitor terminal above is connected to the positive supply plane by way of thermals. That is, it’s connected by three distinct traces, rather than all around the perimeter of the pad. The thermals impose a restriction on heat flow, so that the pad can heat up to proper temp, and the solder can flow and bond correctly. Just like electrical resistance, thermal resistance is proportional to the cross-sectional area of the conductor. Most EDA programs (including Eagle, shown here) will automatically create thermals on pads connected to supply planes, unless you specify otherwise. AFAIK, there is no way to get Eagle to automatically create thermals on vias. Note here that I’m not talking about ‘thermal vias‘, which are something completely different.
So what should you do? The simplest solution is to create your own thermals by running a trace between the pad and the via. It’s not hard — you just have to get over your inclination to make things As Small As Possible. The trace doesn’t need to be very long — the example shown above is actually exaggerated a bit to illustrate the concept. The main idea is that at no point should the via and the pad overlap. The trace shouldn’t be too thin either, especially for a supply pin. Confer with this trace calculator to get a better idea: don’t forget you want to rate the trace for the maximum expected current, not the average current.
A tenth of an inch or two with a trace-width of 12-16 mils should do for most chips. Chips handling larger currents will require larger traces, or multiple small traces — you may end up having to trick your software into doing this by running multiple traces before you place the vias. It might give you grief in the meantime, but just ignore it. In the end, it’s worth it because you’ll have more balanced thermal conduction on your board.
And now you know.
*- There are certain circumstances in which vias-under-pads are necessary and useful, such as with dense BGA packages. In this case the vias have thermals connecting them to the plane for the reasons mentioned above. Chances are, if you’re working with this kind of technology, you don’t need to read my little tutorial here.
Date: 3 July, 2012
Categories: EE - project & practice
I am happy to announce that I am now selling PCBs for my BB-313 project. Since first announcing the design back in February, I’ve gotten several emails a week enquiring about PCBs, so I decided to go for it and start selling them.
These are nice, lead-free boards with a good-quality silkscreen, and they’re available in any color you want, as long as it’s green. Boards are $5/each + $2.50 shipping within the US. International shipping is $5.00 for up to 15 PCBs — this is automatically applied at checkout.
You can read all about the BB-313 at the project page, which also contains a cross-referenced BOM and Mouser project that makes it easy to get all the components required to build one. The BB-313 is Open Source Hardware, so you can make your own boards if you prefer.
Please note that I’m only selling PCBs right now, not kits.
UPDATE: I’ve now got it set up to apply the correct shipping for domestic and international orders, and to accept quantities greater than one.
Date: 13 June, 2012